System and method for integrating a digital core with a switch mode power supply

ABSTRACT

A digital core embodied within a semiconductor die that requires plural separate power supply voltage domains is situated within any of a variety of integrated circuit packaging technologies. Within the integrated circuit package including this semiconductor die also exists a switch mode DC-to-DC voltage converter, preferably a synchronous step-down regulator powering the entire integrated circuit from one supply voltage. The components contained within the integrated circuit package along with the semiconductor die include the switch mode power supply&#39;s power switching transistors, inductor core and windings, digital open-loop output voltage fixing circuitry, output capacitors and substrate for mounting said components when integrated within a packaging technology that does not already include a substrate.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention is generally in the field of semiconductorcircuits. More specifically, the present invention is in the field ofsemiconductor die packaging with integrated power supply voltageregulation.

2. Background Art

Advances in semiconductor integrated circuit fabrication processes anddigital standard cell and semi-custom application specific integratedcircuit, “ASIC”, design methodologies have given rise to digital andmixed analog and digital signal integrated circuits requiring separatepower supplies for various parts including a unique voltage for thedigital core power supply, and a second, unique power supply voltage forthe input/output pad ring, and possibly a third power supply voltage formiscellaneous analog functions. While this advancement brings theadvantage of reduced core power consumption as a product of one-half thetotal gate capacitances times the gate voltages squared times theswitching frequency, there arises the problem of regulation of theseadditional voltages. With the advent of system-on-chip technologies,designers of these devices have only begun to address this requirementfor regulating multiple power supply domains on-chip. Given prior art,it often finally remains the responsibility of the top-level systemintegrator to provide this variety of power supply voltage domains atthe board level and not chip level, obscuring the costs of the totalsolution implementing the prior art system-on-chip. Often both thesystem-on-chip designer and the top-level integrator, not having thetime, resources, or background of experience in power supply design tendto choose simple-to-implement, but less than optimal linear voltageregulation cores or devices to provide these plural voltage domains froma single supply voltage. When implemented using a linear voltageregulation device, a substantial amount of the power savings realized byaccepting a lower core voltage is lost in the form heat dissipatedthrough the linear regulator's transistors, by design. The overallsolution cost and power consumption may actually rise if this heatdissipated in the linear voltage regulator is great enough to requireadditional components to provide forced air convection cooling. Also,the system-on-chip itself could require additional heat-sinkingcomponents or else suffer reduced reliability due to the implementationof a linear voltage regulator on-chip, thereby driving-up hidden costsof the total solution.

Therefore, there exists a need for a novel and reliable system andmethod to provide power to multiple voltage domains of semiconductordies to overcome the problems faced by conventional semiconductor diepackages integrating a linear voltage regulation power supply. Morespecifically, there exists a need for a novel and reliable system andmethod to optimally provide power to multiple voltage domains withinsemiconductor dies while reducing overall system cost, powerconsumption, and heat dissipation.

SUMMARY OF INVENTION

The present invention is directed to a system and method for integratinga semiconductor die of plural power supply voltage domains with a switchmode DC-to-DC converter in an integrated circuit package. The inventiondiscloses a system and a method to design and fabricate such anintegrated circuit system in a single package to obtain optimal powersavings, and minimal heat dissipation and cost. According to oneembodiment, a semiconductor die is situated within the periphery of alead frame adjacent to the switch mode power supply substrate. Thesubstrate can comprise, for example, a ceramic material, or mosteconomically, a fiberglass resin epoxy based laminate material such asFR4. In one embodiment, the semiconductor die is situated on thesubstrate adjacent to the integrated switch mode DC-to-DC converter. Inone embodiment, a semiconductor die may receive power for its lowervoltage supply pads through any DC-to-DC converter of the switch modestep-down variety in a closed-loop general solution implementation.

In the preferred embodiment, the present invention provides a superiormeans for optimally converting voltages to the correct domains forsemiconductor die operation through synchronous step-down conversion.Furthermore, the present invention's substantial departure from priorart and significant novelty exists in the preferred embodiment whereinsaid switch mode synchronous DC-to-DC step-down converter is implementedin an open-loop configuration retaining precision based on semiconductordie power consumption characterization data, thus achieving the lowestpossible cost for total solution of the system-on-chip.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1, including FIGS. 1A and 1B, illustrates ain schematic view andwiring diagramof an , exemplary structure in accordance with oneembodimentembodiments of the present invention.

FIG. 2 illustrates a block diagram of the pulse width modulationcontroller in FIG. 1 according to one embodiment of the presentinvention.

FIG. 3 illustrates a block diagram of the pulse width modulationcontroller in FIG. 1 according to the preferred embodiment of thepresent invention.

FIG. 4 illustrates a schematic view of a switching transistor gatecharge pump circuit according to one embodiment of the presentinvention.

FIG. 5 illustrates a schematic view of a trimmed delay circuit forfine-tuning the duty cycle according to one embodiment of the presentinvention.

FIG. 6 illustrates a schematic view of a physical model of the powerswitching circuit, a graph of electrical current flow through it overtime, and the mathematical derivation of its governing design equations.

FIG. 7 illustrates a perspective view of the complete semiconductor dieand power supply system integrated by bonding within the periphery of alead frame.

FIG. 8 illustrates a perspective view of the complete semiconductor dieand power supply system integrated by bonding upon a common substrate.

DETAILED DESCRIPTION

The present invention is directed to a system and method for integratinga semiconductor die of plural power supply voltage domains with a switchmode DC-to-DC converter in an integrated circuit package. The followingdescription contains specific information pertaining to variousembodiments and implementations of the invention. One skilled in the artwill recognize that the present invention may be practiced in a mannerdifferent from that specifically depicted in the present specification.Furthermore, some of the specific details of the invention are notdescribed in order not to obscure the invention. The specific detailsnot described in the present specification are within the knowledge of aperson of ordinary skills in the art. Obviously, some features of thepresent invention may be omitted or only partially implemented andremain well within the scope and spirit of the present invention.

The following drawings and their accompanying detailed description aredirected as merely exemplary and not restrictive embodiments of theinvention. To maintain brevity, other embodiments of the invention thatuse the principles of the present invention are not specificallydescribed in the present specification and are not specificallyillustrated by the present drawings.

FIG. 1 illustrates a schematic and block wiring diagram of oneembodiment of the present invention. Block 100 represents thesemiconductor die. The semiconductor die 100 may embody any of a varietyof functions that may be implemented using digital standard cell orsemi-custom Application Specific Integrated Circuit “ASIC”, analog oranalog and digital mixed signal design methodologies, any of suchimplementation in said semiconductor die 100 wherein the die itselfrequires plural unique voltage domains for powering its circuitry. Anexemplary embodiment within the semiconductor die 100 could be a digitalcore that performs any of a variety of tasks including genericmicroprocessor tasks, digital signal processing or media stream specificcompression or encoding or decompression or decoding, whereby the coreof the semiconductor die 100 is powered at a lower voltage 102 than itsinput/output pad ring 101. In the preferred embodiment given in thisspecification in only an exemplary and not restrictive manner, thisinput/output pad ring voltage 101, would be that commonly employed inprior art systems, 3.3 Volts, whereas the core voltage 102 would be 1.8Volts, that presently commonly employed in 0.18 micron lithographicprocess geometry based silicon Complementary Metal Oxide Semiconductors,“CMOS”, a well-characterized, mature technology utilizing standard celllibrary based design methodologies. While trends indicate thatresearches are presently pioneering process geometries as small as 90nanometers that entail further reduction in core voltage to below 1Volt, this specification directly exemplifies the mainstream processtechnology in use today and subsequently shows how the present inventionscales well and furthermore, becomes more advantageous as processgeometries reduce and further require reduced core voltages with respectto input/output voltages. This inherent design advantage of the presentinvention only becomes more apparent as lower core voltages are morereadily adopted than lower system-wide input/output supply voltages.

The inherent advantage of the present invention exists due to thefundamental improved efficiency that a switch mode power supply, andespecially a synchronous switched mode power supply has over thelinearly regulated power supply or prior art. For instance, the fieldeffect transistors 103, 104 and mostly the inductor 105 make up thevoltage drop from the input voltage 101 to the output voltage 102 duringthe charging phase of the inductor 105. With the availability of verylow on resistance field effect transistors and the loss of the inductor105 mostly due to the DC resistance of its copper windings which istypically relatively low, most of the energy contained in the voltagedropped across the charging inductor is delivered during the inductordischarging phase of the switching cycle allowing this design to oftenachieve efficiencies greater than ninety percent. In contrast, bydesign, a linear voltage regulator drops all of the difference voltagebetween its input and output voltages across an internal transistor,which burns off the energy in the form of heat, and therefore can neverexceed a power efficiency greater than the ratio of its output voltageto is input voltage, not to mention the adverse affects of the voltageregulator's heat by-product on the life expectancy and performance ofthe semiconductor die. In a traditional, non-synchronous step-downregulator, Schottky diode 113 exists in lieu of bottom transistor 104.While reducing the lost power required to drive the gate of the bottomtransistor 104, because the forward voltage drop across the Schottkydiode 113 is typically greater than the drain-to-source voltage acrosstransistor 104, the efficiency of a traditional step-down regulator isgenerally 5% to 20% less than a synchronous step-down converter.Although this specification subsequently offers a thorough mathematicalanalysis of the operation of a synchronous switch mode step-downDC-to-DC converter, let it now be stated that obviously transistors 103and 104 operate in opposite phase with respect to each other, and greatcare is always necessarily taken in the design of the gate drivers 131,132 to never allow the on periods of these two transistors to coincide,to prevent what is commonly referred to as “shoot-through” current, aneffective short circuit from the input voltage 101 to ground. Since thephase of the switching cycle that transistor 103 is on charges inductor105, then turning off transistor 103 creates a negative change incurrent with respect to time, di/dt<0, this causes the voltage acrossinductor 105 which equals Ldi/dt to reverse, and thus deliver thisreversed electromotive force, or “reverse EMF”, into the output voltagenode 102 as either the now forward-biased Schottky diode 113 ortransistor 104 in the on state in this phase references the formerlypositive, now negative voltage node of inductor 105 to near groundlevel. Implementing both Schottky diode 113 and transistor 104 allowsimproved efficiency as the low forward voltage drop of the Schottkydiode 113 references the discharging phase negative node of inductor 115105 to ground after transistor 103 turns off but before transistor 104turns on, with ample delay to prevent shoot-through current. Let it beknown that any combination of components implemented whether transistor104 or Schottky diode 113 or both, does not constitute a substantialdeparture beyond the scope of the present invention.

The following components comprise the feedback loop common to nearly allexisting step-down switch mode power supplies and therefore couldconstitute any implementation within the scope of the present inventionalthough such a traditional feedback loop does not comprise the outputvoltage fixing circuit found in the preferred embodiment practicedwithin the preferred method of the present invention. All Referring toFIG. 1A, all the discrete components external to the semiconductor die100, including resistors 114, 115, 116, 118, capacitors 117, 119, 120,and substrate bonding pads 121, 122, and the components internal to thesemiconductor die 100, including the bonding pads 123, 124, the band-gapvoltage reference 126, the reference voltage buffer 127, and the erroramplifier 125 of FIG. 1 1A, and the voltage comparator 200, depicted inFIG. 2 within the pulse width modulation controller 129, exist in afeedback loop in common practice of prior art switch mode DC-to-DCconverters, but this feedback loop does not exist in the output voltagefixing circuit found in the preferred embodiment practiced within thepreferred method of the present invention, as shown in FIG. 1B.Nonetheless, since the circuitry of the prior art feedback loop does notconstitute a substantial departure beyond the scope of the presentinvention, its use will hereinafter herein be briefly described.

The two resistors 114 and 115 form a voltage divider that allowsarbitrary setting of the output voltage 102 given the fixed internalreference voltage presented at the output of the reference voltagebuffer 127 into the error amplifier 125. This output voltage 102 canthen be arbitrarily fixed to any value given by the reference voltagemultiplied by the quantity of one plus the ratio of resistor 114 overresistor 115. Resistors 116 and 118 and capacitors 117, 119, 120 formthe frequency compensation of the error amplifier 125 within thefeedback loop of the traditional switch mode power supply. While tuningthese frequency compensation components is not germane to thespecification of the present invention and is elsewhere covered ingreater detail, this specification will now disclose some generalobservations regarding it. Uncompensated, the inductor 105 and theoutput capacitor 106 produce a complex pole pair at their resonantfrequency given by one over the quantity of two times π times the squareroot of inductance times the capacitance. The output capacitor 106 alsoplaces a zero above the pair of poles at a frequency given by one overthe quantity of two times π times the capacitance and the value of thecapacitor's 106 equivalent series resistance, “ESR”. Generally as a goalin compensation, two zeroes are added near the filter resonant frequencyto correct the sharp change in phase near that frequency and anopen-loop unity gain frequency is chosen to exist at a frequency aboutten times greater than the resonant frequency but less than about 10% ofthe switching frequency. The overall gain of the error amplifier 125,the filter components comprising the inductor 105 and output capacitor106, the two zeroes added plus the gain of the integrator in thecompensation network that sets open-loop unity gain frequency should sumto zero at the unity gain frequency. The integrator gain is given by1/(2π(F_(o))(R114(C119+C120))) where F_(o) is the open-loop unity gainfrequency. The frequency of the output filter compensating zeroes equals1/(2π(R118)(C120)) and 1/(2π(R114+R116)(C117)) and these zeroes areunderstood to add to 40 dB per decade of gain. A pole also exists in thecompensation network and its frequency is chosen to coincide with thezero formed by the output capacitor 106 and its equivalent seriesresistance “ESR”. This compensating pole frequency equals1/(2π(R116)(C117)). A final pole in the compensation network exists atthe frequency 1/(2π(R118)(C119∥C120)) and is selected to be about¾F_(s), three-quarters of the switching frequency to reduce switchingnoise into the comparator 200. While it is understood the preciseplacement of the pole frequencies, integrator frequency and zeroesfrequencies is not of utmost criticality, care must still be taken tofollow the aforementioned feedback loop frequency compensation practicesto give best power supply response and stability over widely varyingloads. In the past, stability problems have risen due to substitutingthe output capacitor 106 such as with the choice of a ceramic capacitorof very low ESR to replace a capacitor of differing material andconstruction incurring higher ESR, thus the compensation network nolonger providing proper phase margin and causing the instability. In thepreferred embodiment not only is this dilemma avoided, furthermore bynot including such feedback and compensation network and preferablyincluding a very low ESR ceramic output capacitor 106, it achievesefficiency improvement, lowest output voltage ripple, and space savings.The frequency compensated feedback loop provides a general solutionwhere load is not well characterized, or effectively a system to controla stochastic process. Obviously, the addition of components 114 through127 and component 200 adds significant cost to an integrated circuit.The components mounted on the power supply substrate have obvioustangible cost, but also the analog components internal to thesemiconductor die 100 add expense in terms of process precisionrequirements resulting in lower yield compared to an implementation ofstrictly digital standard cell library components. Thereforesubsequently this specification presents a novel preferred embodimentand method of design and manufacture wherein the cost of a frequencycompensated feedback loop is avoided by characterizing the powerrequirements of the semiconductor die 100 and thus simplifying thesystem to a deterministic input model.

One motivation in using such a frequency compensated feedback loop asidefrom its field proven robustness to a widely varying load, is that oftenin digital cores and especially mixed signal cores, there may alreadyexist a band-gap voltage reference 126 for any of a variety of analogfunctions, or in the former case of a digital core, for use in aphase-lock loop analog macro cell whereby the digital core is clocked ata much higher rate than is driven by, although derived from, theexternal clock source. While an integrated circuit product of long lifeor high unit volume expectancy would lose significant profit byincurring the cost of the components needed for a frequency compensatedfeedback loop versus the preferred embodiment and method, if thesemiconductor die 100 already contains a band-gap reference 126 and thecost of fully characterizing the power states of the semiconductor diein terms of time-to-market of a short-lived product outweighs theadditional cost of the frequency compensated feedback loop andadditional reference voltage buffers 127, error amplifier 125 andcomparator 200, then the traditional switch mode power supply solutionmay be desirable.

The remaining components in FIG. 1 include the pulse width modulation orpulse frequency modulation controller 129 which will be furtherdelineated in subsequent paragraphs and in FIG. 2 and FIG. 3, the output130 of the modulation controller 129 that feeds the gate drivers 131,132 and the related power-up sequencing and under voltage lock out logic134 and associated components. As shown for logical clarity, a singleoutput 130 of the modulation controller 129 inputs to both gate drivers131, 132. As previously mentioned, the gate drivers 131, 132 must bedesigned with consideration given to the turn-on and turn-off delay ofthe power switching field effect transistors 103, 104 such that the twotransistors 103, 104 are never on simultaneously. This may beaccomplished in the preferred embodiment by providing through,preferably but not necessarily, synchronous means, a delay of one gatedriver turning its transistor off for approximately 40 nanosecondsbefore the other gate driver turns on its transistor. Therefore theoutput 130 of the modulation controller 129 may actually comprise bothlogic and synchronization signals or exist as two differing signals ofsimilar phase only delaying the rising edge into driver 131 and delayingthe falling edge into driver 132. Another consideration for these gatedrivers 131, 132 is the switching frequency F_(s) and thus the totalcurrent that driving the total gate charge of transistors 103, 104requires at this frequency, preferably obtainable by implementing a12-to-16 milliamp or less driver output pad cell common to most standardcell libraries. A thorough analysis of the gate drivers 131, 132 will bedisclosed along with the exemplary power supply components commerciallyavailable for the preferred embodiment subsequently with the descriptionof FIG. 6 and the derivation of the governing design equations. Block134 represents the logic employed in power-up sequencing and undervoltage lock out functions. Pad 133 would likely be implemented as a lowtrue reset input that an external power supervisor module outputsconditionally from monitoring the input/output ring voltage 101. Onpower-up, upon arriving at a satisfactory voltage level for a prescribedperiod of time, the external supervisor brings the reset signal on pad133 to an inactive state. As shown in FIG. 1, if the reset signal is lowtrue the logic block 134 may simply route this directly to the positivetrue output enable inputs of the gate drivers 131, 132. Ultimately thelogic block 134 is also responsible for proper power-up and power-downsequencing of the other internal functional blocks of the semiconductordie 100, including the internal clocking circuitry and thus the pulsewidth modulation or frequency modulation block 129, and this may beachieved by simply giving proper delay to the input reset signal frompad 133 before routing to other remaining functional blocks within thesemiconductor die 100. As such, under voltage lock out is essentiallythe function provided by the external power supervisor circuit, theresult is identical regardless of power-up or power-down. When the resetsignal 133 is active due to under voltage of the input/output pad ringvoltage 101, the gate drivers 131, 132 are placed into high impedancestate, and the resistors 107, 108 bring the power switching transistors103, 104 into an innocuous off state. While portrayed in FIG. 1 asexternal resistors 107, 108, the same exact functionality may beobtained through the use of two 10-to-100 microampere current sourcesconfigured as default weak pull-up and weak pull-down, respectively,standard cell output pads internal to the semiconductor die 100.

FIG. 2 illustrates a block diagram of the pulse width modulationcontroller 129 for implementation within the aforementioned frequencycompensated feedback loop. The analog comparator 200 receives at itsinverting input, the voltage signal output 128 from the error amplifier125. The non-inverting input 201 of the analog comparator 200 receives aDC voltage signal equal to that of the voltage reference 126, in thesame manner as the error amplifier 125, through a unique instance of avoltage follower, separate but equal to that of the voltage buffer 127.In this manner as stated previously, the single instance of the voltagereference 126 may serve a plurality of functions, including but notlimited to also an analog phase-lock loop for internal clocking of adigital core, through a plurality of unique instances of voltage buffersequivalent to buffer 127. Thus the analog comparator 200 compares theinverted output 128 of the error amplifier 125 to a DC reference voltage126. Since the comparator 200 itself is also configured as an invertingamplifier referenced to the band-gap voltage reference 126, the powersupply output voltage 102 once divided by resistors 114, 115 getsinverted through the error amplifier 125, and its output 128 getsinverted by the comparator 200, thus the comparator output 202 is alogic high signal when the output voltage 102 is above the set voltageand the comparator output 202 is a logic low signal when the outputvoltage 102 is below the set voltage. This comparator output 202 logicsignal is routed out through an Or gate 203 to a common D flip-flop 211into its positive true asynchronous reset input. Thus when the outputvoltage 102 exceeds the set voltage, the D flip-flop 211 isasynchronously reset and its inverted output 130, also the output of themodulation controller 129 and inputs to both gate drivers 131, 132, goeshigh, disabling the top power switching transistor 103. Routing thiscomparator output 202 to the asynchronous reset input of the D flip-flop211 permits the controller 129 to operate in an energy saving “pulseskip” mode. When the output voltage 102 exceeds the set voltage, theenergy needed to charge and discharge the power switching transistorgates is saved.

The pulse frequency portion of the controller 129 depicted in FIG. 2begins with the clock circuit 204. This clock may be the buffered inputof a clock source external to the semiconductor die 100, or an output ofan internal clock generation circuit such as a phase-lock loop. Theoutput 205 of this clock circuit then feeds a frequency dividing clockcounter 206. This counter 206 may either count up to a terminal value orcount down from an initial value that divides the clock output 205 downto the power supply switching frequency, F_(s), in the range of 100 KHzto 2 MHz, and in the preferred embodiment, approximately 1 MHz duringpeak load current. The counter 206 outputs count values on bus 207 to adecoder 208. In the implementation employing a frequency compensatedfeed back loop, this decoder 208 strictly decodes the states prior tothe counter roll-over and outputs a rising edge signal 210 to clock theD flip-flop 211 upon each roll-over of the counter 206 at the powersupply switching frequency, F_(s), and also outputs a pulse signal 209that goes active high then inactive low one clock 205 state prior to theroll-over of counter 206, through an Or gate 203 into the asynchronousreset input of the D flip-flop 211. The pulse signal 209 thus affectsthe D flip-flop 211 to go into a reset state just prior to the end ofthe period defined by the power supply switching frequency, F_(s), andbecause the D flip-flop 211 is configured with its inverted output 130feeding back to its D input, the D flip-flop 211 then toggles uponreceiving a clock pulse 210. As long as the analog comparator output 202is not causing a pulse skipping constant asynchronous reset state of Dflip-flop 211, this guarantees the output 130 causes gate driver 132 todrive power switching transistor 103 active at the beginning of theperiod defined by the power supply switching frequency, F_(s), with amaximum duty cycle defined by the number of count values counted on bus207 minus one divided by the total number of count values counted on bus207.

FIG. 3 illustrates a block diagram of the pulse width or frequencymodulation controller 129 for implementation within the preferredembodiment of the present invention. As before, the output 205 of clockcircuit 204 feeds a counter 206 that derives the power supply switchingfrequency, F_(s), and duty cycle through decoder 208, with D flip-flop211 responding exactly as before to signals 209 and 210 to form theoutput 130 that feeds the gate drivers 131, 132. The difference in thecontroller 129 of the preferred embodiment compared to the previouslydescribed implementation employing the frequency compensated feedbackloop, is the absence of the Or gate 203 including the output 202 of thecomparator 200 for asynchronously resetting the D flip-flop 211, andalso the addition of alternative output voltage fixing circuitry. Thispreferred embodiment of the pulse width or frequency modulationcontroller 129 achieves the significant cost-saving goal of eliminatingall power supply related analog components internal to the semiconductordie 100, the voltage buffers 127, the error amplifier 125, and theanalog comparator 200, through the use of what may be implemented withall digital standard cell library components. Instead of feeding back anerror voltage signal through a comparator 200 to fix the output voltage102, by characterizing the semiconductor die 100 current consumptionover process variations and operating environment temperatures in allpower states knowing its fixed input and output supply voltages 101,102, values for power supply duty cycle and/or switching frequencyF_(s), relative to various supply current states may be implemented indecode logic configurations, or stored in registers or memory locationsas depicted by block 303 in FIG. 3, and thus fix the power supply outputvoltage 102 precisely. The theory behind and method for implementingthis innovation is described in subsequent paragraphs referencing FIG.6. Therefore in the preferred embodiment, the operation of decoder 208is slightly modified with respect to producing the duty cyclecontrolling pulse signal 209. Decoder 208 in the preferred embodimentnow compares the frequency dividing clock count on bus 207 to a value onbus 305 that represents a duty cycle value corresponding to the presentpower state of the semiconductor die 100, theoretically calculated thenempirically verified through probe testing the power supply substrate,that obtains the correct output voltage 102 by resetting D flip-flop 211by asserting pulse signal 209 at the correct time. In one embodimentwithin the scope of the present invention, the values corresponding tovarious power states contained within block 303 may be encoded withinthe logic of decoder 208. In alternate embodiments within the scope ofthe present invention, block 303 may be a non-volatile memory deviceexternal to the semiconductor die 100, with values programmed aftercharacterization of the semiconductor die 100 and after probe testingthe power supply substrate, that get downloaded into register spacewithin semiconductor die 100 during reset. In yet another alternateembodiment within the scope of the present invention, block 303 maystore values corresponding to the power supply switching frequency,F_(s), while also varying or keeping fixed the duty cycle to obtain thecorrect output voltage 102 by decoding values on bus 207 within decoder208 and outputting signals 209 and 210 appropriately.

Between the output bus 304 of block 303 and bus 305 into decoder 208 inFIG. 3 exists an arithmetic logic unit 302 that takes binary offsetvalues from pads 300 input onto bus 301 and either adds these to orsubtracts these from the values stored in block 303 output on bus 304before inputting the sum or difference into decoder 208 from bus 305.The hypothetical use of this offset is that in some embodiments of thepresent invention, the values stored in block 303 overestimate thetheoretical losses in the power supply components and once verifiedempirically by probe testing the power supply substrate at variousoutput current levels, the precise output voltage 102 is obtained byreducing the duty cycle and/or switching frequency, F_(s), by the amountrepresented by the offset value, the binary number input on pads 300. Ifthe frequency divider clock counter 206 counts up, the arithmetic logicunit 302 subtracts the value on bus 301 from the value on bus 304, andconversely, if counter 206 counts down, the arithmetic logic unit 302adds the value on bus 301 to the value on bus 304, in order to reducethe duty cycle or switching frequency, F_(s), to obtain the empiricallytested precise output voltage 102. The binary number offset input onpads 300 may be implemented in any of the following ways. The pads 300may be optionally bonded to the input voltage 101 or ground rail or padsof a lead frame or die mounting substrate, with a default internal weakpull-down or pull-up embodied within the pad 300. In another embodimentof the present invention the pads 300 may be bonded to a substrate andthe binary number offset may be encoded by breaking fusible leads on thesubstrate either through mechanical or electrical or laser-trimmingmeans during integrated circuit assembly, as before with a defaultinternal weak pull-down or pull-up embodied within the pad 300. Let itbe known that minor deviations or omissions, partial or completenon-implementation of this offset adjusting mechanism does notconstitute a substantial departure beyond the scope of the presentinvention.

FIG. 4 depicts a switching transistor gate charge pump circuit generallyimplemented to improve the efficiency of the power switching circuit. InFIG. 4, the N-channel enhancement mode field effect transistor 403replaces the P-channel enhancement mode field effect transistor 103 inFIG. 1. While the circuit of FIG. 4 costs an additional five smallcomponents, the advantages include a lower current gate driver 132;economy of scale cost reduction by now ordering twice as many N-channelswitching transistors 403, 104; and for equivalent structures with equalgate-to-source voltage magnitudes and total gate charges applied,N-Channel devices tend to have a drain-to-source on resistance of aboutsixty percent of that of P-Channel devices, due in part to electronmobility being greater than hole mobility in silicon. As shown, when inthe inactive state, transistor 402 is on, turning off power switchingtransistor 403, transistor 404 is off and capacitor 400 is charging upto the input voltage 101 minus the sum of forward voltage drop of theSchottky diode 401 and the drain-to-source voltage of the transistor 104not shown. When in the active state, transistor 403 turns on bytransistor 402 turning off, allowing the gate of transistor 403 to firstcharge through resistor 405, then as transistor 404 turns on, the gateof transistor 403 rises above the input voltage 101 by approximately thevoltage stored across capacitor 400, bringing the transistor 403 to avery low on resistance state. Resistor 107 functions exactly as it didin FIG. 1, holding the circuit in an innocuous state when driver 132 isin a high impedance state. This charge pump circuit is portrayedstrictly in an exemplary and not restrictive manner, therefore any othercircuit achieving the same results does not constitute a substantialdeparture from the scope of the present invention.

FIG. 5 illustrates a trimmed delay circuit for fine-tuning the dutycycle of the power switching transistor 103. While this circuitnecessitates the addition of four or five more components, theadvantages include a reduced current gate driver 132; and when theaddition of bonding pads 300 incur greater expense in semiconductor diearea than the cost of the additional components, the elimination ofbonding pads 300 needed to set a binary number offset for lowering thetheoretical duty cycle on the semiconductor die 100. The circuit of FIG.5 shortens the duty cycle by providing an asymmetrical delay, bydelaying the turn-on, but not the turn-off of power switching transistor103, attached by its gate lead to the lead 500. Bipolar NPN transistor503 goes into saturation when adequate current flowing into its basereaches a voltage of between 0.65 to 0.7 Volts. In order for the base oftransistor 503 to arrive at the saturation voltage, capacitor 502 mustcharge through resistor 501 fed from the voltage present on substratebonding pad 109, delivered by the gate driver 132. This voltage onsubstrate bonding pad 109 is approximately equal to the input/output padring voltage 101, referred to in equations as V_(in) hereinafter.Therefore according to the first-order linear model for chargingcapacitors, the on period of the power switching transistor 103 isreduced by a maximum of—(R501)(C502) In(1−07/V_(in)) seconds and aminimum of—(R501)(C502)In -(R501)(C502) In(1−0.7/V_(in)) seconds and aminimum of -(R501)(C502) In (1−0.65/V_(in)) seconds. The turn-off ofpower switching transistor 103 is not significantly delayed becauseSchottky diode 504 quickly follows the voltage of substrate bonding pad109 as it drops, immediately discharging capacitor 502 to no more thanthe Schottky diode 503 forward voltage, well below the saturationvoltage of transistor 503. By including transistor 503 in the path ofthe gate driver signal, the polarity of the gate of power switchingtransistor 103 is now effectively inverted. Therefore to implement thiscircuit compared to the previously described embodiments, the gatedriver 132 should now invert its input signal 130 prior to outputtingthe signal from die bonding pad 111 onto substrate bonding pad 109.Resistor 107 must exist external to the semiconductor die 100 in thisembodiment, which may or may not have been implemented as such inpreviously described embodiments, and must now provide current in theorder of tens of milliamps to avail the appropriate gate charging timesfor the desired switching frequency, F_(s), instead of microamperes ofholding current as previously described.

As with the binary number offset pads 300, the hypothetical use of thedelay circuit of FIG. 5 is that in some embodiments of the presentinvention, the values stored in block 303 overestimate the theoreticallosses in the power supply components and once verified empirically byprobe testing the power supply substrate at various output currentlevels, the precise output voltage 102 is obtained by reducing the dutycycle by a percentage equal to the amount of time of the delaymultiplied by the switching frequency, F_(s). While the amount of delaytime has an accuracy of approximately +/−20% depending upon componenttolerances, the total amount of duty cycle error, and thus outputvoltage 102 error, is ultimately reduced to ordinarily less than 2%since the total delay itself is a small fraction of the total dutycycle. The manufacturer of the integrated circuit may employ any of atleast two methods of trimming this delay. Insertion of a 1% tolerancesurface mount resistor 501 on the power supply substrate may occur afterthe aforementioned probe test through a selective pick-and-placeprogram, or preferably, resistor 501 may exist as a printed filmresistor on the power supply substrate prior to the aforementioned probetest and trimmed by laser to set the desired output voltage 102. Lasertrimming works especially well because not only may the manufacturerperform this simultaneous to probe testing, but also as previouslydiscussed, the theoretical duty cycle may be estimated at a levelgreater than practical, and printed resistors, while being trimmedincrease in resistance. Therefore the trimming of the resistor 501 bylaser while simultaneously probe testing, raises its resistance, whichincreases the time delay of switching on the power transistor 103, whichshortens the duty cycle, thus converging from above to the preciseoutput voltage 102 most expeditiously.

One other advantage of the circuit in FIG. 5 is it avails the integratedcircuit designer flexibility in choice of power switching transistor 103and in design of the gate driver 132. With implementing the delaycircuit of FIG. 5 on the power supply substrate, the designer mayaccommodate large variability in two parameters otherwise affectingdesign of the gate driver 132, the turn-on delay and total gatecapacitance of the power switching transistor 103, after thesemiconductor die 100 has been designed and fabricated.

TABLE 1 Kirchhoff's Voltage Law, Kirchhoff's Voltage Law, 103 on, 104off (dt1): 103 off, 104 on (dt0):$0 = {V_{in} - {I_{o}\left( {R_{{DSon}\quad 1} + R_{LDCR}} \right)} - {L\frac{\mathbb{d}i}{\mathbb{d}t_{1}}} - V_{o}}$$0 = {{L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}} - {I_{o}\left( {R_{{DSon}\quad 2} + R_{LDCR}} \right)} - V_{o}}$${\therefore V_{o}} = {V_{in} - {I_{o}\left( {R_{{DSon}\quad 1} + R_{LDCR}} \right)} - {L\frac{\mathbb{d}i}{\mathbb{d}t_{1}}}}$${\therefore V_{o}} = {{L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}} - {I_{o}\left( {R_{{DSon}\quad 2} + R_{LDCR}} \right)}}$

${\therefore{L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}}} = {V_{o} + {I_{o}\left( {R_{{DSon}2} + R_{LDCR}} \right)}}$Choose L, Fs such that |di| < 2(Io_((min))) for continuous modeoperation, (for this analysis to apply)${{\therefore V_{o}} = {{V_{in} - {I_{o}\left( {R_{{DSon}\quad 1} + R_{LDCR}} \right)} - {L\frac{\mathbb{d}i}{\mathbb{d}t_{1}}}} = {{L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}} - {I_{o}\left( {R_{{DSon}\quad 2} + R_{LDCR}} \right)}}}};$𝕕i_(𝕕t₁)=  𝕕i$V_{in} = {{L{{\mathbb{d}i}}\left( {\frac{1}{\mathbb{d}t_{1}} + \frac{1}{\mathbb{d}t_{0}}} \right)} + {I_{o}\left( {R_{{DSon}\quad 1} - R_{{DSon}\quad 2}} \right)}}$SwitchingFrequency ≡ F_(s) = 1/(𝕕t₁ + 𝕕t₀)$V_{in} = {{L{{\mathbb{d}i}}\left( \frac{{\mathbb{d}t_{0}} + {\mathbb{d}t_{1}}}{\mathbb{d}{t_{1}\left( {\mathbb{d}t_{0}} \right)}} \right)} + {I_{o}\left( {R_{{DSon}\quad 1} - R_{{DSon}\quad 2}} \right)}}$DutyCycle ≡ δ = 𝕕t₁F_(s)∴ 𝕕t₁ = δ/F_(s)$V_{in} = {{L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}\left( \frac{1}{\delta} \right)} + {I_{o}\left( {R_{{DSon}\quad 1} - R_{{DSon}\quad 2}} \right)}}$${\therefore{L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}}} = {\delta\left( {V_{in} - {I_{o}\left( {R_{{DSon}\quad 1} - R_{{DSon}\quad 2}} \right)}} \right)}$${L\frac{{\mathbb{d}i}}{\mathbb{d}t_{0}}} = {{\delta\left( {V_{in} - {I_{o}\left( {R_{{DSon}\quad 1} - R_{{DSon}\quad 2}} \right)}} \right)} = {V_{o} + {I_{o}\left( {R_{{DSon}2} + R_{LDCR}} \right)}}}$

FIG. 6illustratesand Table 1 illustrate a schematic view of a physicalmodel of the power switching circuit, including losses, a graph of theoutput current versus time, and the mathematical derivation of theequations that govern the design of the system. The mathematicalderivation begins with a time domain piecewise linear analysis applyingKirchhoff's Voltage Law for the two phases of when the top transistor103 is on and charging the inductor 105, and then when the bottomtransistor 104 is on referencing the inductor 105 to ground as itdischarges. This approach affords two independent equations from whichto derive an expression for: the output voltage 102, hereinafterreferred to as V_(o), as a function of the input voltage 101, V_(in);the duty cycle, δ, lower case delta; the theoretical losses, namely theDC resistance of the inductor 105 coil, R_(LDCR) 600, and thedrain-to-source on resistances of the switching transistors 103, 104,R_(DSon1) and R_(DSon2) respectively; and the average output current,hereinafter referred to as I_(o). Note that I_(o) is a sum of theaverage current demanded as the semiconductor die 100, and thepeak-to-peak inductor 105 ripple current, referred to as di. It is knownthat CMOS digital devices require current mostly during switching, andthe instantaneous current demand can appear as a pseudo random pattern,so therefore, the semiconductor die 100 supply current may be thought ofas a statistical average of random instantaneous currents. Thisstatistical average works well as voltage regulation is the ultimategoal, and the output capacitor 106, especially one of very low ESR,delivers instantaneous peak currents as needed to provide a constantaverage voltage with little noise and ripple voltage. This analysisyields extremely accurate results providing adherence to the criterionof continuous mode of operation, assuming the turn-on and turn-offdelays of the switching transistors necessary to prevent shoot-throughcurrent do not represent a significant portion of the switching period,1/F_(s). The criterion of continuous mode operation may be explainedqualitatively by stating that as long as current continually flowsthrough the inductor 105, the system behaves in continuous mode; , ormay be described graphically, and thus derived mathematically, by notingthat if the trough of inductor ripple current sawtooth waveform, di,dips to the x-axis, its lower limit, then operation becomesdiscontinuous, (or in other words, the lower half of the ripple current,di/2, must be less then the average output current, in mathematicalterms, di<2I_(o(avg.)) for continuous mode operation). Since themathematical derivation depicted in FIG. 6Table 1meticulously indicatesall algebraic manipulations performed in arriving at the governingequations, one skilled in the art needs no description of this treatmentto appear here in the text of this specification. Block 601 shows theresult of the analysis, V_(o) as a function of V_(in), duty cycle,I_(o), and losses. Block 602 shows a representation of peak-to-peakinductor ripple current, di, as a function of transistor 103 on-time, dt1;₁, inductance L, V_(in), V_(o),I_(o), and top transistor 103drain-to-source on resistance, R_(DSon1), and Inductorinductor coil DCresistance 600, R_(LDCR). The equation in block 601 and its derivativeverifies the assertion of the fundamental theoretical principle of thepresent invention, namely, given fixed input and output voltages 101,102, and having characterization data defining all supply current statesI_(o), with empirical data or even reasonably accurate estimates statingthe component losses, one may digitally fix the duty cycle of a highefficiency synchronous switch mode power supply in an open loopconfiguration and still obtain a precise output voltage 102, whileeliminating the expense of the frequency compensated feedback loop andespecially the precision analog circuits internal to the semiconductordie 100.

A brief description of a design method followed by a practical designexample including commercially available switch mode power supply partswill further illustrate the above stated theoretical assertion. Thepreferred design and fabrication method comprises the following designmethod that applies to the preferred embodiment and therefore any otherembodiments within the scope of the present invention may entail certaindeviations to the following method that also remain within the scope ofthe present invention. Upon completing the design of the core within thesemiconductor die 100, the integrated circuit designer has availablepower consumption estimates per clocking rates and ambient temperatureand process variations, from the integrated circuit design automationtools. From this point the designer may fix certain system parameterssuch as acceptable system clocking rates, thus defining clock sourceparameters, and from here arrange the number of power states along withthe actual power consumed by the semiconductor die 100 in each of thesestates. Given this data, the designer may complete the top-level designof the semiconductor die 100, including designing the power supplycomponents comprising the gate drivers 131, 132; the power-up sequencingand under voltage lock out logic 134 along with its interaction with theclock circuit 204; and the entire pulse width or frequency modulationcontroller 129 while defining the configuration of and values containedwithin the duty cycle or frequency table 303. Referring to the equationwithin block 601 within FIG. 6, the designer may estimate the desiredduty cycle or switching frequency, F_(s), which are interchangeable dueto their direct proportionality as shown elsewhere in FIG. 6, bymanipulating the equation within block 601 solving for duty cycle as afunction of V_(in), V_(o), I_(o), and the loss components from thephysical model. Next in the design procedure, after determining suchparameters as the frequency of the clock source 204, duty cycles perI_(o) states and especially the lowest current state I_(o(min)), thedesigner may now select inductance values L, and switching frequencies,F_(s), as dictated by the equation given in block 602 and the continuousmode criterion. Note at this point that parameters of the switchingtransistors 103, 104, total gate capacitance and turn-on and turn-offdelay, also affect both the choice of switching frequency, F_(s), anddesign of the gate drivers 131, 132. The accuracy of the applied dutycycle values determine the precision of V_(o), and obviously theaccuracy of the dependent variables affect the calculation of these dutycycle values. V_(in) is likely regulated to within 2% of its idealvalue, and I_(o) often calculated as a worst case, overestimated by upto 20%. As shown in block 601, the error voltage dependent on I_(o) isalso a product of the loss components which generally the designer canestimate from graphs such as drain-to-source on resistance versusgate-to-source voltage and drain-to-source on resistance versus draincurrent plus the DC coil resistance given as a maximum value in inductoror inductor core vendors' datasheets, resulting in a resistance in therange of 100 hundred milliohms and is of such proportions as to reducethe affect of the I_(o) estimation error. This yields a total I_(o)current dependent error voltage ordinarily less than two tenths of aVolt for most semiconductor die, which often is within the supplyvoltage tolerance. Nevertheless, the preferred method prescribesperforming a physical characterization of the semiconductor die 100,empirically determining I_(o) per clocking rates and ambient temperatureand process variations; and also a probe test of the power supplysubstrate at different duty cycles and load currents corresponding tothe various I_(o) states to determine V_(o) at each of these states,perhaps in a statistical sampling manner during production, butcertainly during prototyping of the power supply substrate. Theintegrated circuit manufacturer should consider the last steps duringmanufacture, i.e. probe testing the power supply substrate at variousoutput currents, I_(o), to determine the extent of trimming the voltagefixing circuit, preferably when the estimated or empirically found totalI_(o) current dependent error voltage represents a significant portionof the V_(in) supply voltage tolerance. If the total estimated I_(o)current dependent error voltage does not represent a significant portionof the V_(in) supply voltage tolerance, then not only these last stepsin manufacturing may be skipped, the entire aforementioned outputvoltage offset adjusting circuits of FIG. 3 or FIG. 5 may be foregonefor additional savings in the manufacture of the semiconductor die 100,or the power supply substrate itself.

The discussion now turns to a brief design example including selectionof commercially available power supply components. This design examplerepresents one of many configurations within the scope of the presentinvention and should be viewed as exemplary, not restrictive. Forinstance, this design example utilizes off-the-shelf transistors intheir available packages, whereas using devices purchased through aknown-good-die program and installed on the power supply substrate usingchip-on-board technology would improve the use of power supply substratearea, but not substantially deviate beyond the scope of the presentinvention. In this example, a digital core has been designed thatperforms the function of a microprocessor that operates in threedifferent power states, high speed, low speed, and idle, from a singleexternal clock source or internal crystal oscillator specified togenerate a 25 MHz input clock. The semiconductor die that embodies thismicroprocessor is fabricated in 0.18 micron CMOS technology and requiresa 1.8 Volt +/−10% core voltage and a 3.3 Volt input/output ring voltageThe design automation tool estimated the supply current drawn from thecore voltage supply pads at 1 Ampere in high speed operation, 500 mA inlow speed, and 100 mA in idle. First the designer chooses the powerswitching transistors 103, 104 primarily based on the criterion ofhaving a very low drain-to-source on resistance given the approximate3.3 Volt gate-to-source voltage that may be driven from the pads 111,112 of the semiconductor die 100, with its 3.3 Volt input/output padring voltage. The designer chooses the Si5513DC available from themanufacturer Vishay Siliconix. The reasons for choosing this very smallpackage of dual complementary transistors include its lowdrain-to-source resistance at a gate-to-source voltage magnitude of 3.3Volts at a drain current of 1 Ampere, approximately 85 milliohms for theN-channel Field Effect Transistor 104, and 150 milliohms for theP-channel Field Effect Transistor 103; its relatively low typical totalgate charge of around 4 nano-coulombs at a gate-to-source voltage of 3.3Volts which a standard cell 16 mA gate driver 131, 132 can easily sinkand source current for a switching frequency of up to 2 MHz; andrelatively fast turn-on and turn-off delays of no worse than 40 nS.Other transistors exist with better drain-to-source on resistances atthat magnitude of gate-to-source voltage which would improve the powerefficiency, but the trade-off would be higher total gate capacitancewhich may warrant larger gate drivers 131, 132; longer delay times whichwould increase the output voltage error; and the Si5513DC is packaged ina single unit of the standard form factor of the Electronic IndustriesAlliance, “EIA”, 1206 package where the others are in separate packages,doubling the area required on the power supply substrate. From thispoint, the designer may now determine the design of the gate drivers131, 132, and set a nominal switching frequency, F_(s), of 1 MHz, whichimplies the frequency divider clock counter 206 should count up from 0to the count 24 if directly fed from the clock source 204 generating a25 MHz clock. Now the designer, referring to block 601 of FIG. 6, alsomay determine the values stored in block 303 for use by the decoder 208equate to 14, the fifteenth state of clock counter 206, for a duty cycleof 59.5% with less than 1% error for the microprocessor in high speed;13, the fourteenth state of clock counter 206, for a duty cycle of 57.0%with 1.8% error for the microprocessor in low speed; and 13 for a dutycycle of 55.0% with 1.8% error for the microprocessor in idle. Thesecount values represent the full on-time for transistor 103, and theturn-on and turn-off delays of the transistors may be accommodated byturning on transistor 104 one clock 204 state later, and off one clock204 state earlier, while its body diode would continue to reference thereverse EMF of inductor 105 to ground during these delay periods. Sincethe values within block 303 adequately compensate such that 20%over-estimation error of both I_(o) current and loss components valuescan cause only about 4% output voltage error, but since the error due tothe turn-on and turn-off delays of the transistors 103, 104 equate toabout 2.4% and magnetic core loss could make an additional 2% of outputvoltage error, both in the opposite direction, the designer may foregoimplementing any of the aforementioned output voltage error offsetadjusting circuits as depicted in FIGS. 3 or 5, for this example design.Otherwise, because the switching frequency, F_(s), is derived directlyfrom a clock that runs at twenty fives times F_(s), the duty cyclegranularity is 4% and therefore the offset adjusting circuit of FIG. 5would be better at reducing the total output voltage error below 4%compared to that of FIG. 3. Knowing the I_(o(min)) value allows thedesigner to calculate the limit for maximum inductor ripple current, di,dictated by the continuous mode criterion then determine the minimuminductance by manipulating the equation in block 602 of FIG. 6, solvingfor L. In this design example, this calculation yields a value of 4.1micro Henries for L. A value of 4.7 micro Henries is chosen for L andthe inductor core manufacturer of choice, Micrometals, Inc., can providethe toroid core, the lowest cost part number T20-52, that after windingwith 18 turns of 28 gauge solid copper wire can sustain this inductanceat 1 Ampere and about 5.6 micro Henries at 100 mA, with a DC resistanceof 37 milliohms in a package that sits at 0.1 inches height and 0.228inches outside diameter. This enables continuous mode operation of theswitch mode power supply down to currents typically as low as 73 mA.With increasing the switching frequency, F_(s), continuous modeoperation is guaranteed down to an output current inverselyproportionally lower, although as stated before, increasing F_(s) causesmore power to be consumed in the gate drivers 131, 132. At twice theswitching frequency, 2F_(s) (nominal), this exemplary circuit remainscontinuous for a semiconductor die 100 drawing as little as 36 mA, butthe gate drivers 131, 132 alone consume an amount of power equal to acore voltage 102 drawing 30 mA, thus diminishing the savings of such anidle state. The only remaining component that the designer needs tospecify now is the output capacitor 106 which preferably may beimplemented with a 10 micro Farad ceramic capacitor of X5R temperaturecoefficient dielectric material presently available also in the EIA 1206package type. This type of capacitor typically has an ESR of a few tensof less than ten milliohms and thus the ripple voltage, a product of theripple current multiplied by this capacitor's ESR, will be less than 5milliVolts. Therefore this exemplary circuit integrating a digital corewith a high efficiency switch mode voltage regulator comprising asemiconductor die and three low profile packages could fit well withinthe confines of many packaging technologies, especially the presentlypopular Ball Grid Array or the Plastic Quad Flat Pack standard formfactors of the Joint Electron Device Engineering Council.

FIG. 7 and FIG. 8 render a perspective view of a physical embodiment ofthe previously described design example within the scope of the presentinvention. Power supply substrate 703 and likewise substrate 800 mayconsist of a ceramic material, an organic material such aspolytetrafluoroethylene material, or most commonly a fiberglass resinepoxy based laminate material such as FR4. In FIG. 7, the power supplysubstrate 703 and the semiconductor die 100 sit adjacent to each otherwithin the periphery of a lead frame 700 for assembly within a leadedpackage. In FIG. 8, the power supply components are mounted on the samesubstrate 800 as the semiconductor die 100, the practice of mounting asemiconductor die directly to a substrate as such being common to BallGrid Array packages of prior art. In both of these two exemplaryembodiments, the toroid core inductor 105, the package containing thepower switching transistors 103, 104, and the output capacitor 106 arefirst mounted to the substrate. In any of the methods within the scopeof the present invention, once these components are mounted to thesubstrate, the substrate may be probe tested at various load currentsand duty cycles corresponding to the power states of the semiconductordie 100, and then trimmed according to any of the previously describedoutput voltage offset adjusting systems or methods. According to theembodiment of FIG. 7, the bonding pads of the power supply substrate 703and the semiconductor die 100 are then first affixed to the lead frame700 by bonding wires 706 and 708, respectively, attaching to lead framebonding pads 707 and 701, respectively, and then interstitial bondingwires 704 attach the bonding pads 702 of the semiconductor die 100 tothe bonding pads 705 of the power supply substrate 703. The presentinvention places no restriction upon the signal types conducted via theinterstitial bonding wires 704, they may conduct any of the power supplyspecific signals or also simply any signals conveniently routed to theside of semiconductor die 100 in the location of bonding pads 702,across the interstitial bonding wires 704, and routed directly frombonding pads 705 across the power supply substrate 703 to the powersupply substrate pads nearest the lead frame bonding pads 707. Afteraffixing all of the interstitial bonding wires 704, the device may thenbe sealed with an epoxy in a ceramic body or molded in a plastic bodyand undergo final test. In FIG. 8, as with the embodiment of FIG. 7,once the supply components 103, 104, 105, 106 have been mounted andoptionally tested and trimmed, bonding wires 802 affix the semiconductordie 100 to the substrate 800 and permit electrical and perhaps heatconduction from the bonding pads 702 of the semiconductor die 100 to thebonding pads 801 of the substrate 800. The top surface of the substrate800 may then be sealed with an epoxy or molded over with a plastic bodyand undergo final test. In the case of a Ball Grid Array package, thebottom surface of the substrate 800 contains pads that in the final stephave solder balls attached.

From the preceding description of the present invention it is manifestthat various techniques can be used for implementing the concepts of thepresent invention without departing from its scope. Furthermore, whilethe invention has been described with specific reference to certainembodiments, a person of ordinary skill in the art would recognize thatchanges could be made in form and detail without departing from thescope and the spirit of the invention. The described embodiments havebeen presented in all respects as illustrative and not restrictive. Itshould also be understood that the invention is not limited to thepreviously described particular embodiments, but is capable of manyrearrangements, modifications, omissions, and substitutions withoutdeparting from the scope of the invention.

Thus, a system and method for integrating a digital core with a switchmode power supply has been described.

1. An integrated circuit package, comprising: a semiconductor die ofplural separate power supply voltage domains; and a switch mode DC-to-DCconverter, comprising: wherein said switch mode DC-to-DC convertercomprises: an inductor core and windings; a power switching transistor;and an output voltage fixing circuit comprising a digital open-loopmeans circuit configuration requiring no feed-forward loop and nofeedback loop.
 2. An integrated circuit package, comprising: asemiconductor die of plural separate power supply voltage domains; and aswitch mode DC-to-DC converter, comprising: wherein said switch modeDC-to-DC converter comprises: an inductor core and windings; a powerswitching transistor; and an output voltage fixing circuit, wherein saidsemiconductor die comprises a decoder that compares an entry from atable corresponding to the present power state of said semiconductor dieto a clock counter frequency divider output to determine a duty cycleand/or switching frequency of said power switching transistor for saidoutput voltage fixing circuit.
 3. The integrated circuit of claim 2,wherein said table of entries of clock counter values used to determinesaid duty cycle is encoded within logic within circuitry of saidsemiconductor die.
 4. The integrated circuit of claim 2, wherein saidtable of entries of clock counter values used to determine said dutycycle is contained within non-volatile memory.
 5. The integrated circuitpackage of claim 2, wherein the a power transistor gate-driving signaloutput from said semiconductor die is connected through a charge pumpcircuit to optimize the efficiency of the power switching transistor ofsaid DC-to-DC converter.
 6. The integrated circuit package of claim 2,further comprising a substrate of fiberglass resin epoxy of type FR4based FR4-based laminate material for mounting components of saidDC-to-DC converter components .
 7. The integrated circuit package ofclaim 6, wherein said semiconductor die further comprises a plurality ofpads from which to accept a binary number offset for fine tuning saidduty cycle and/or switching frequency by modifying the value said tableentry being compared to the clock counter frequency divider in output bysaid output voltage fixing circuit of said DC-to-DC converter.
 8. Theoutput voltage fixing integrated circuit package of claim 7, whereinsaid binary number offset is embodied included within fusible leads onsaid substrate that are electrically or mechanically trimmed orlaser-trimmed at the factory .
 9. The output voltage fixing integratedcircuit package of claim 7, wherein said binary number offset isembodied included within a an optional wire-bonding option duringassembly of said plurality of semiconductor die pads to the lead frameof said integrated circuit package.
 10. The integrated circuit packageof claim 6, wherein the a power transistor gate driving that drivessignal output from said semiconductor die is connected through a trimmeddelay circuit to fine tune the duty cycle of a pulse width modulator orpulse frequency modulator of the output voltage fixing circuit of saidDC-to-DC converter.
 11. The output voltage fixing integrated circuitpackage of claim 10, wherein said trimmed delay circuit furthercomprises a laser-trimmed printed film resistor on the substrate that islaser-trimmed at the factory .
 12. An integrated circuit package,comprising, a substrate of fiberglass resin epoxy of type FR4 g basedlaminate material for mounting: ; a semiconductor die of plural separatepower supply voltage domains mounted on said substrate; and a switchmode DC-to-DC converter further comprising an inductor core andwindings, mounted on said substrate, wherein said switch mode DC-to-DCconverter comprises: a power switching transistor; and an output voltagefixing circuit comprising a digital open-loop means circuitconfiguration requiring no feed-forward loop and no feedback loop. 13.The output voltage fixing integrated circuit package of claim 7, whereinsaid binary number offset is embodied included within a an optionalwire-bonding option during assembly of said plurality of semiconductordie pads onto a said substrate of fiberglass resin epoxy of type FR4based FR4-based laminate material.
 14. A method for design andfabrication of an integrated circuit package comprising a semiconductordie of plural separate power supply voltage domains with an integratedswitch mode power supply, said method comprising steps of : designing asemi-custom or standard cell library based digital core and obtainingfrom the design automation tools power consumption estimates in variouspower states given known clocking rates; determining switch mode powersupply frequency, inductance, and duty cycles for various power statesgiven said power consumption estimates and system clocking; fabricatingsaid semiconductor die for prototyping purposes, packaged without saidintegrated switch mode power supply; characterizing said prototypesemiconductor die for power consumption over all operating power statesand environmental conditions and process variations; fabricating saidswitch mode power supply onto final production substrates; trimming theoutput voltage fixing circuit of said switch mode power supply after aprobe test to determine the output voltages at given duty cycles versusoutput currents defined by said semiconductor die known characterizationdata; and bonding and molding or sealing with epoxy said semiconductordie and power supply substrate into an integrated package.
 15. Themethod of claim 14, wherein said step of trimming the output voltagefixing circuit further comprises a step of binning said final productionpower supply substrates into the appropriate wire-bonding assembly lineto set the proper binary number offset of the output voltage fixingcircuit.
 16. The method of claim 14, wherein said step of trimming theoutput voltage fixing circuit further comprises a step of breakingfusible leads on said final production power supply substrate to set thebinary number offset of the output voltage fixing circuit.
 17. Themethod of claim 14, wherein said step of trimming the output voltagefixing circuit further comprises a step of laser trimming a printed filmresistor forming a delay circuit of the output voltage fixing circuit onsaid final power supply substrate.
 18. The method of claim 14, whereinsaid step of trimming the output voltage fixing circuit furthercomprises a step of programming a non-volatile memory with entries ofclock counter values to determine duty cycle and/or switching frequencycorresponding to each power state of the semiconductor die.
 19. A methodfor design and fabrication of an integrated circuit package comprising asemiconductor die of plural separate power supply voltage domains withan integrated switch mode power supply, said method comprising steps of: designing a semi-custom or standard cell library based digital coreand obtaining from the design automation tools power consumptionestimates in various power states given known clocking rates;determining switch mode power supply frequency, inductance, and dutycycles for various power states given said power consumption estimatesand system clocking; fabricating said semiconductor die for prototypingpurposes, packaged without said integrated switch mode power supply;characterizing said prototype semiconductor die for power consumptionover all operating power states and environmental conditions and processvariations; fabricating said switch mode power supply onto finalproduction substrates; and bonding and molding or sealing with epoxysaid semiconductor die and assembled final power supply substrate intoan integrated package.
 20. A semiconductor die comprising a decoder thatcompares an entry from a table corresponding to a present power state ofsaid semiconductor die to a clock counter frequency divider output todetermine a duty cycle and/or switching frequency of at least one powerswitching transistor for an output voltage fixing circuit of a switchmode DC-to-DC converter.
 21. The semiconductor die of claim 20, whereinsaid table used to determine said duty cycle is encoded within logiccircuitry of said semiconductor die.
 22. The semiconductor die of claim20, wherein said table used to determine said duty cycle is containedwithin non-volatile memory.
 23. The semiconductor die of claim 20,further comprising: at least one pad from which to accept a binarynumber offset for fine tuning said duty cycle and/or switchingfrequency, wherein said fine tuning operates by modifying said tableentry being compared to the clock counter frequency divider output bysaid output voltage fixing circuit of said DC-to-DC converter.
 24. Thesemiconductor die of claim 23, wherein said binary offset is a binaryoutput of at least one analog comparator.
 25. A method of design of apower supply for an integrated circuit, comprising: determining a priorcharacterization of power consumption over all operating power states,environmental conditions, and process variations of said integratedcircuit; and providing as said power supply an output voltage fixingcircuit that retains precision based on said determined powerconsumption characterization data of said integrated circuit.
 26. Theintegrated circuit package of claim 1, wherein said switch mode DC-to-DCconverter further comprises an inductor core and windings.
 27. Anintegrated circuit package, comprising: a semiconductor die of pluralseparate power supply voltage domains; and a switch mode DC-to-DCconverter, comprising: a power switching transistor; and an outputvoltage fixing circuit comprising a digital open-loop circuitconfiguration that retains precision based on power consumptioncharacterization data of said semiconductor die.
 28. The integratedcircuit package of claim 27, wherein said switch mode DC-to-DC converterfurther comprises an inductor core and windings.
 29. The integratedcircuit package of claim 2, wherein said decoder compares an entry froma table, said entry based on power consumption characterization data andcorresponding to the present power state of said semiconductor die, tothe clock counter frequency divider output to determine a duty cycleand/or switching frequency of said power switching transistor for saidoutput voltage fixing circuit.
 30. The integrated circuit package ofclaim 12, wherein said substrate is fiberglass resin epoxy of typeFR4-based laminate material.
 31. The integrated circuit package of claim12, wherein said switch mode DC-to-DC converter comprises an inductorcore and windings.
 32. An integrated circuit package, comprising: asubstrate; a semiconductor die of plural separate power supply voltagedomains mounted on said substrate; and a switch mode DC-to-DC convertercomprising: a power switching transistor; and an output voltage fixingcircuit configured to retain precision based on power consumptioncharacterization data of said semiconductor die.
 33. The integratedcircuit package of claim 32, wherein said switch mode DC-to-DC converterfurther comprises an inductor core and windings.
 34. The integratedcircuit package of claim 32, wherein said output voltage fixing circuitcomprises a digital open-loop circuit configuration requiring nofeed-forward loop and no feedback loop.
 35. The integrated circuitpackage of claim 32, wherein said substrate is fiberglass resin epoxy oftype FR4-based laminate material.
 36. The semiconductor die of claim 20,wherein said table entries are based on power consumptioncharacterization data and correspond to the present power state of saidsemiconductor die.
 37. The semiconductor die of claim 24, wherein saidat least one analog comparator enables operation of said DC-to-DCconverter in an energy-saving pulse skip mode.
 38. The integratedcircuit package of claim 2, wherein said switch mode DC-to-DC converterfurther comprises an inductor core and windings.